Harald Lorenz

Responsible for yield/product quality grade improvement on high volume product. Define/maintain yield and quality roadmaps and drive continuous improvement projects to ensure Top-Tier customer requirements. Work closely with process integration team on yield/quality improvement topics (using FMEA, Kepner Tregoe). Analyze non-conforming material for product disposition and root cause identification. Currently focusing on development support for leading edge technology node introduction into manufacturing.

Product portfolio analysis; IP research in motion control market

Lead international product and test engineering development team for a custom design DRAM product. Definition of DfT features, planning and tracking of product and test engineering work packages. Achieved qualification of low power DDR product ahead of schedule despite reduced staffing. Supported and executed concept and feasibility studies for low power DDR/DDR2 products based on advanced technology nodes. Key contributor to secure MobilDDR business resulting in significant cash generation.

Established CellularRAM known good die 'KGD' business. Responsible for planning and tracking of design verification on multiple DRAM development projects. Design analysis and characterization expert for DRAM products. Team leader for design analysis group. Founding member of Infineon's memory development site in Vermont. Defined equipment to be purchases and supervised setup of bench lab at new development center.

Lead engineer of design analysis bench team working on advanced DRAM products. Achieved successful Intel validation for 256M DDR 266.

Failure analysis (new designs and customer returns), technology/process evaluation and circuit modification using leading edge equipment (SEM, EMMI, FIB). Responsible for training of 30+ FA engineers (Munich, Dresden, Malaysia, Taiwan). Development of new FA preparation techniques (paper presentation at ISTFA 1998).