Hardik Shah

At fortiss, I am a reseacher in the field of Multicore Architectures. The contribution is to provide a concept of Predictable and High Performance multicore architecture. Apart from doing research, I am representing the company promotional events like International fairs, supervising master students, writing research proposals for securing funding and taking part in inter continental projects.

My activity at TES includes support to the customer site projects in the fields of Hardware Development, Verification and Documentation.

My responsibility at Nero was to develope hardware IPs for Advance Audio Codec decoder in Xilinx FPGA. Optimization of various software decoders, development and maintenance of Audio Plug-ins were the tasks full filled in the software department.

At IHP, I was responsible for hardware/software partitioning of the IEEE 802.15.3 MAC protocol and development of the hardware accelerator in Xilinx FPGA.

Embedded Systems, SoC Architecture, Digital Design with HDL, Design of Digital Integrated Circuits, Submicron Digital Circuits Design, Electronic System Packaging, System Modelling, Design of Fault Tolerent Systems, ASIC Design methology with High Level Languages.