Ioannis Seitanidis

The main focus of the internship was the development of a novel methodology to compose registers (single or multi-bit) into new multi-bit registers (MBRs). This approach has been integrated into Mentor’s Nitro place-and-route tool.

Floorplan exploration of digital IP blocks with the evaluation of their power consumption, area, congestion, regarding network-on-chip architectures. Parameterized model development for predicting the aforementioned design quality metrics.

Highest honors: 9.26/10 – Ranked 1st in his class Thesis: “Network-on-Chip routers with time-shared resources”