Jiawei Zhong

• Work closely with senior & principal engineers to deliver cutting edge HDL & deep learning code generation compiler product with Java/Matlab/C++. • Develop IR-based code generation features to leverage and integrate HDL compiler engine into real applications, e.g. hardware-software co-design on SoC platform and deep learning acceleration on FPGA. • Manage and mentor small group of interns, junior development & QA engineers in India office.

• Develop and implement comprehensive test frameworks for HDL Coder compiler workflow, from Matlab/Simulink modeling, HDL code generation till hardware on-board testing • Develop and maintain automated hardware testing infrastructure on Xilinx Zynq & Altera SoC platforms. • Develop software test plans & unit tests per release to achieve 85%+ code coverage, execute sweep testing, regression testing & manual bash to identify the root cause of bugs.

• Work in Ethernet consortium to develop the first 40G Ethernet conformance testing tool for UNH-IOL. Design 40G Ethernet PCS IPs with Verilog to deploy on Altera Stratix-IV FPGA platform.