Jill Arenasa

30+ yrs Global Eng. Leader|Cost Opt. & Tech|Open to roles (Salary negotiable)

Bis 2026, Senior Lead Engineer - Cost Technology Optimization, Lear Corporation
Lapu-Lapu City, Philippinen

Fähigkeiten und Kenntnisse

Engineering
Technology
Circuit design
Electronics
Systemengineering
Electrical Engineering
Globalisation
Management
Commitment
Technical Knowledge
Leadership

Werdegang

Berufserfahrung von Jill Arenasa

  • 2 Jahre und 9 Monate, Feb. 2024 - Okt. 2026

    Senior Lead Engineer - Cost Technology Optimization

    Lear Corporation

    Led Cost Technology Optimization (CTO) for Asia Non-China vehicle programs to drive product and process savings without sacrificing quality or safety. Appointed in Jan 2025 to head Europe CTO Support and Global QIE Support teams, governing global cost initiatives. Directed VA/VE, should-cost modeling, and competitive analysis. Partnered with cross-functional global teams and suppliers to boost sourcing value and build team capabilities.

  • 9 Jahre und 1 Monat, Jan. 2015 - Jan. 2024

    Senior Lead Engineer - Electrical Benchmarking

    Lear Corporation

    Scaled global benchmarking function from inception to 100+ engineers; built industry-leading analysis frameworks. Deployed global analysis tools for standardized, cross-division competitive intelligence. Led ICE/EV teardowns, testing materials via FTIR/XRF to drive strategic platform roadmaps. Managed end-to-end procurement, tracking budgets with Finance to optimize costs and technical compliance. Delivered technical reports to VP-level stakeholders and trained global engineers on HV wiring.

  • 8 Jahre und 1 Monat, Jan. 2007 - Jan. 2015

    Vehicle Electrical Systems Engineer | OIC Supervisor

    Lear Corporation

    • Lead electrical architecture design for low- and high-voltage global vehicle platforms. • Develop advanced electrical solutions optimizing cost, performance, and manufacturability. • Collaborate with OEM customers to align system specs with commercial requirements. • Drive RFI/RFQ technical processes, deliver cost data, and pioneer benchmarking specs. • Create schematic diagrams using Capital Logic, Cabling Designer, and MS Visio.

Ausbildung von Jill Arenasa

  • 11 Monate, Juni 2016 - Apr. 2017

    Electronics and Communication Engineering

    University of San Jose–Recoletos

    As an ETEEAP graduate in Electronics and Communications Engineering, I hold a degree earned through a specialized Philippine government program validating my work experience. Backed by competency assessments and over 30 years of practical field experience, I possess a solid background in automotive wiring. I excel in circuit analysis, applying strong problem-solving skills to real-world engineering issues while maintaining a commitment to continuous learning.

Sprachen

  • Chinesisch

    A1-A2 (Grundkenntnisse)

  • Deutsch

    A1-A2 (Grundkenntnisse)

  • Englisch

    C2 (Verhandlungssicher / Muttersprachlich)

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