Jochen Hupfer

Design Service Electronics & Measurement Protoyping MSR & Automation, Sensors Sucess Story: Projects on electronics, design study's, prototypes, programming, technology service, Sensors, ESP32

responsible for the development of a fiber-based synchronization unit (fronthaul SDR receiver network) for a new real-time Puck&Player Tracking system. Design Flow from early requirement analysis, system design and prototype to production. This giving the Fraunhofer Team a boost of positioning accuracy for Puck&Player tracking during the NHL 2018 All-Star Game and winnig the Joseph von Fraunhofer Award in 2019. https://www.youtube.com/watch?v=MKkkMhfRJQ0

Senior Design Engineer responsible for System-Integration, Hardware/Embedded/FPGA, System Maintenance FPGA/Embedded/SoC for SDR-localization platforms (Xilinx, Zync, CPLD, RPI) MATLAB/Simulink, SYSgen, fiber-channel ADC synchronization concepts. Education and team integration, students and new team members. Full support Fraunhofer Algorithm-Team Education support and team integration of students and new team members. https://ieeexplore.ieee.org/document/7362649

Technical project manager charging & programming hub for Puck&Player RF-ID-Tags Responsible for the development of a wireless charging and programming system for Puck&Player Tags Jogmo Eco-System

As the sub project manager I was responsible for field installation within ARENA Nürnberg. Sight view, coordination material and trades, ramp up system, system performance check, LWL infrastructure and SDR Radio-Heads. As well technical system support for Fraunhofer Research Team Integration of system modifications Education new Team-members Coordination external Suppliers

As Design Engineer FPGA and Algorithm Simulation Consulting and Research for industrial R&D projects Matlab/Simulink Algorithm verification (FPGA,DSP) Algorithm verification with hardware in the loop and Matlab/Simulink RF-Systems, SDR-Multiplatform FPGA, FPGA-Antenna-Unit, as well Metering Systems

As System Design Engineer responsible for integration and implementation of the 3G Radio Head project This giving a unique multi-platform SDR with reuse in lots of further Fraunhofer projects

Responsible for simulation, implementation various R&D sensor signal processing. Interdisciplinary work within the Fraunhofer IC-Design Team responsible for design study, algorithm implementation with VHDL (FIR IIR CIC Filter Design, State Machines ) in various R&D projects for sensor signal processing. Work on Industrial Research Projects. Automatic VHDL code generators 0.35u AMS RF-Transmitter Mixed Signal Chip for RTLS-System