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Jose Suarez

Angestellt, Validation Engineer, Infineon Technologies Austria AG, Villach
Abschluss: System Desing - Embedded Systems:, Fachhochschule Kärnten - Carinthia University of Applied Sciences
Villach, Österreich

Fähigkeiten und Kenntnisse

Advanced driver assistance systems
Functional Safety
Verification and validation
FPGA
Embedded Systems
VHDL
MatLab
Test Automation
Test and Measurement
Instrumentation
Networks
Industrial electronics
Interface
SQL
System
Softwareentwicklung
Database Management
PCB design systems
ADAS
C/C++
Altium
Advace Design Systems (software)
Python

Werdegang

Berufserfahrung von Jose Suarez

  • Bis heute 4 Jahre und 4 Monate, seit Feb. 2021

    Validation Engineer

    Infineon Technologies Austria AG, Villach

  • 1 Jahr, Feb. 2020 - Jan. 2021

    Information Professional

    Financiera Coomultrasan

    I am managing and updating the client database using SQL queries with Oracle and DB2 software. Additionally using python software to ease data management. Reporting information according to client requirements and giving the information in agreement to data personal treatment. Creating reports to check and update data quality indicator to improve them.

  • 1 Jahr, Okt. 2018 - Sep. 2019

    Verification Engineer - Master Thesis

    Infineon Technologies Austria AG, Villach

    FPGA-based Interface for Advanced-Diver-Assistance-Systems (ADAS): I developed a hardware/software interface for ADAS application using the flexibility of an FPGA. For FPGA-ADAS connectivity, I designed a PCB expansion using Altium Designer and ADS for Signal Integrity analysis. I used VHDL and Matlab design - hardware/software to automate the test-cases. The FPGA-based interface was in charge of checking safety standards, such as ISO26262, by means of different hardware/software scenario configurations.

  • 1 Jahr und 10 Monate, Okt. 2016 - Juli 2018

    Verification Engineer - Intern

    Infineon Technologies Austria AG, Villach

    Clock Interface System - SERDES - ADAS Application: I participated in the Post-silicon verification of CIS modules. Examples include jitter and phase noise measurements of PLL modules, including PVT variation based on design specifications. Furthermore, I was responsible for the verification of an ADAS interface.

Ausbildung von Jose Suarez

  • 2 Jahre, Sep. 2017 - Aug. 2019

    Master of Science in Engineering

    Fachhochschule Kärnten - Carinthia University of Applied Sciences

    I attended several lectures with HW/SW implementation tools. The most interesting projects were related with the use of FPGA, microcontrollers, and other devices, which required use of different software such Matlab, Visual C/C++, Vivado and LabView for analogue and digital signal analysis.

  • 3 Jahre und 6 Monate, Juli 2013 - Dez. 2016

    Electronic Engineering

    Universidad Pontificia Bolivariana

    Automation and control, telecommunications, microelectronics, biomedical engineering, Systems and signal.

Sprachen

  • Spanisch

    Muttersprache

  • Englisch

    Fließend

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