Karsten Stangel

DDR/Integrated VR - Analog circuit design for next generation server processors.

- LargeSignalArray Register File design for microprocessor building blocks at multi GHz operation. - On-die power delivery prototyping and modeling. Analysis of power supply noise induced jitter for IO interfaces - Design of a DDR3 interface in 32nm technology for a many core processor. Member of a design team located in Austin, Portland, Hudson and Braunschweig - Feasibility study and exploration of QPI - Specification and definition of a high speed DRAM interface

- Design of a PCI-Express Gen1 interface for Playstation3 in 70nm CMOS process - Low power PCI-Express Gen1 receiver in 70nm CMOS technology - Design of an asynchronous 1.0-1.4Gbps SerDes receiver and transmitter including 1-bit De-Emphasis transmitter equalization - Low-power asychnronous digital 622Mbps IO for SDH/SONET in 140nm and 110nm CMOS technology

- Design of a very low-power wake-up circuit for transponder systems - Transponder ASIC design of pressure measuring system utilizing on-chip sensor capacitors

Mikroelektronik