Mahmoud Tohmaz

FPGA design for Optical Network testing devices

FPGA Engineer for Network Interfaces

VHDL design of a 4x4 MIMO detector supporting up to 64 QAM modulation schemes and based on breadth-first-search tree search criterion. ASIC implementation of the designed detector using a 65 nm technology process for checking the core area required and the clock speed performance

RTL design and implementation of an advanced one-node-per-cycle architecture of a two-stage pipelined 4x4 MIMO sphere decoder supporting up to 256 QAM modulation schemes. Development of a fixed point C++ model of the designed sphere decoder for testing and debugging purposes. Master Thesis: "Architecture Implementation of an Advanced Sphere Decoder"

Testing and Debugging of a new Formal Verification tool (FCK) developed by the Embedded Systems Research Group

Learned a new Formal Verification methodology "Complete Interval Property Checking". Designed and verified the core controller of a DDR2 memory interface to an existing FPGA- based-System-On-Chip computing platform

Microelectronics and Embedded Systems