Manivannan Thangamani

Design of adaptive equalizer in 55 nm CMOS technology - Behavioural modelling of high speed data-paths blocks. - Block level simulations and evaluation. - Sub-blocks transistor-level prototyping. Practicing design skills using Cadence Virtuoso IC 6.

The design of an All-digital VCO-based ADC in 65 nm technology - Different architecture exploration and suitable architecture choice for implementation. - Design implementation of ADC in time-domain. - System-level abstraction and transistor-level design. Simulation for high-speed design using Cadence IC6 and frequency spectrum analysis using Matlab.

Design of passive sigma delta modulator in 0.35 um CMOS technology - Full-custom analog design for idea to fabrication. - Top-down design methodology includes modeling, circuit and layout-levels. - Pre/Post-silicon design, simulation, verification and validation (LVS, DRS and PVT). Design sent for foundry and chip evaluation by handling measurement equipment such as Signal Generator, Oscilloscope and Spectrum analyzer.

Course study: Advance VLSI Design, Analog/Digital System Design, Radio Electronics, Radio Frequency Integrated Circuits, Radio Frequency Transceiver Design, Digital Integrated Circuits, and Application-Specific Integrated Circuits