Muhammad Adil Saeed

Designed the framework for using the hashing algorithms and finding the data from the huge buckets. (C, C++) Designed the Risc-v assembler that supports the RV-32(I and M) extension. It also detects and find the errors. Some minor errors are replaced by the assembler too.

Designed and developed training material for the UVM methodology. Worked on AXI protocol and Cocotb. Successfully completed all assigned tasks on time. Learned new technologies and adapted to the environments. Developed strong communication and teamwork skills.

Learned different tools QUESTA, QUARTUS etc. Learned the UVM methodology by scratch and implemented the referenced models using the python. BFMS, Verilog, System Verilog, Coverage enhancement, python scripting. Designed and developed Verification Intellectual Property (VIP) for the peripherals UART, SPI, GPIO, TIMER and PWM. Developed VIP for the DECODER and ALU block using UVM. Demonstrated strong problem-solving and analytical skills.

Worked on design and implementation of a RISC-V microprocessor based System-on-chip (SOC).

Digital Logic design, Microprocessor systems, Computer Architecture, Digital Logic design, Industrial process control Final Year Project: "Development of Verification IP for RISC-V based IPs"