Muhammad Ali Faizan

Digital Design and Verification of ASICS Keywords: Systemverilog, UVM, Top Level Verification, Block Level Verification, Covergroups and SVA

Topic: Hazard Detection Framework Tasks and Steps: 1) Development of GUI for Schematic Generation of the pruned combinatorial logic 2) Development of Algorithms for Reconvergence 3) Development of a methodology for analyzing static and dynamic hazards on gate level 8) Design of MATS+ MBIST Architecture in Verilog and evaluation of tool on the synthesized netlist

1) Development of Verilog Netlist Parser in Python 2) Development of Cell Library Parser in Python 3) Pruning the net specified by the user and backtrack the combinatorial part until all source nodes are found. 4) Assigning levels to the pruned combinatorial logic

Working Student in the PMIC group

- Digital Design - Real Time Embedded Systems and Security - Mixed Signal Design - Electrical Design Automation