Nagaramya Jayagopal

Topic : Timing Monitoring in Digital CMOS Circuits An approach to measure the Timing slack using Razor FFs to detect timing failures and methods of correcting them. Tools :Cadence Virtuoso schematic and layout, Titan SPICE Simulation, VHDL design

Development of hardware and firmware (Embedded C for ARM Cortex M) for microphone array, for USB streaming of audio data and application development in Wake on Voice libraries from Malaspina. Hardware architecture of a Kitchen Assistant Robot and also Bus systems for multi-board communication.

Schematic design, providing placement inputs and guidelines to the PCB layout team, net list verification and release for board building. (Mentor Graphics) Rapid proto board development and testing. Following the DO-160 design guidelines for Aero Electronic Hardware. Through-hole to SMD and cost take out analysis for existing Avionics products.

Schematic design, Library parts creation, Simulation of discrete logics in the board, layout design, Gerber generation using Altium Designer PCB design Software. Benchmarking of components for obsolete Parts. Implementation of design logic and writing test benches in VHDL (using Xilinx ISE Design Suite 12.4). Preparation of documents: PHAC, EHRD and PDRD for various boards which is required for DO-254 certification of the AEH

Grade offered: 1.72 , Masters in Embedded Systems and Microelectronics Project: Development of Intelligent Display system for Formula Student car with NIOS II core SOC design on Max 10 FPGA