Pankaj Gode

- Working on CoreCLR (Common Language Runtime with JIT based compiler) for Qualcomm’s ARM64 server processor by identifying optimization opportunities, architecture specific tuning and optimized JIT helper functions. - Submitted patches to github link https://github.com/pgodeq

- Worked on LLVM compiler for ARM64 processor by identifying, planning, implementing optimizations and submitting patches. - Submitted patches for processor architecture specification, peephole optimizations and tuning target specific optimizations. Contributions are available at https://reviews.llvm.org/search/query/UKjU8Rmp__to/#R

- Improved LLVM compiler backend for reconfigurable processor with register file port conflict checking feature, for input assembly file. - Developed LLVM based synchronous data flow programming model for multi-core SRP platform, by simplification of concurrent programming with implicit and deterministic concurrency specification. - Created LLVM based Random Diagnostic Generator tool, which generates user constrained and scheduled MCInst, for processor architecture verification.

- Worked on LLVM compiler for SRP, by improving function inlining optimization with customized cost function, which in combination with loop unrolling gives 3% gain. - Enabled C++ source input to LLVM infrastructure for SRP, by adding, missing dynamic memory support and function pointer support.

C2RTL compiler optimization, loop transformations and code generation optimizations. Team leading. Dynamic simulator generation framework development.

Performance analysis of processor architecture simulators

Advanced computer architecture, Digital Imaging, Software architecting, Graph Theory