Ravi Kiran Tirupathi

Technical Manager for cross disciplinary R&D team responsible for Established GigE camera Portfolios: Manta, Mako & GT series. Firmware Technical Lead supporting core FPGA & uC development and bring up of Sony IMX sensor series for established portfolio. Scrum Architect providing Technical support to Product Owner & Scrum Master.

Complex Electronics Hardware (CEH) Level Requirements Engineering with DOORS on DO 254 compliant FPGA/CPLD designs. Developer Level Configuration Management via DIMENSIONS involving Source Control, Version Control, Base Lines, Releases, Problem Report (PR), Change Request (CR). Design & Code (VHDL) Review targeting Xilinx Virtex, Spartan & Cool Runner II series. Performed FPGA level "Formal Validation" for SOI2 phase for MTR390 Tiger Helicopter "Engine Control & Monitoring Unit" Project.

FPGA Design and Development (VHDL) in compliance with ISO 13485 Medical standard. Functional Verification (Simulation) and Hardware Unit Tests (Test) Quartus II Suite, Modelsim, Altera Stratix II GX & Arria II GX FPGAs Matlab, C, Tcl, Linux Shell Scripts. PCI Express, I2C, SPI Digital Image Processing Interfacing ADC, DAC, Clock Buffers, Power Rail Sensor, Temperature Sensor. Power Up and Reset sequence, Clocking Scheme

Characterizing sensitivity of setup & hold measurements and also cell delay & slew measurements w.r.t. process parameters variation for Standard cell libraries (90nm) and hence appending a Sensitivity Look Up Table (LUT) to the existing cell library (90nm). (Tools: C++, Virtuoso Spectre Circuit Simulator, MS Excel). Parser for Synopsys Standard cell library (tcbn90g). (Tools: C++). SPICE Deck Lab - Delay computation for a specific Timing Path chosen from the Netlist. (Tools: Perl, Spectre).

Teaching Electronics Devices and Circuits (EDC), C++, VHDL.

VHDL on Xilinx Virtex FPGA, Embedded C

Projects in C, C++