Ronny Schneider

GDDR5/5X/6 graphics DRAM design and verification; team lead

GDDR5 graphics DRAM Design & Verification, team lead

Design of a high speed GDDR5 graphics DRAM interface managing tight interface timings for up to 6Gbps in 2 technology nodes (full chip verification, block design in VERILOG, redesign)

Head of design team for a DDR2 DRAM shrink (to 90nm) with responsibility for 16 engineers, chip implementation and evaluation. Training of design team members (all new hires, fresh from university). Technical expert for x/ydec, global control, redundancy, full chip verification.

Design of DDR DRAM circuit blocks in 110nm technology (ydec, redundancy). Design of DDR2 DRAM blocks in 110nm technology (global control, redundancy, full chip verification). Design verification, layout and layout verification. Support of analysis and evaluation at probe station in test lab. Redesigns comprising design and layout.

theoretical and applied physiks; computer science (minor); thesis: noise measurements on single-electron-transistors