Soja Sasi

Design and Implementation of a combined FPGA and software real time audio engineering solution for implementing Chinese Digital radio transmitter in a general-purpose signal generator.

Re-Design of UDP/IP module to introduce 10Gbps support in Intel Stratix 10 device to fully utilise the Intel proprietary Ethernet MAC IP Core. Implementation of IGMP version 3 (RFC3376) on Intel Stratix 10 FPGA with NIOS II processor with FreeRTOS running.

3D mathematical modelling in Blender, a 3D modelling tool using Python scripting.

I have nearly 4 years of experience in developing IP/Ethernet based transport features for back-end infrastructure of 3G/4G core networks. I was mainly involved in the design and implementation of transport functionalities and its corresponding GUI interfaces in C/C++. I have created build scripts (makefiles) and automated test scripts in shell scripting( BASH) for testing overall transport functionalities.

Master Thesis: Design and Implementation of a combined FPGA and software for implementing Chinese Digital radio transmitter in a general-purpose signal generator.

Advanced Microprocessors, Electronics Circuits Design, Digital Communication, VLSI