Soumyajit Sinha

Topic : Technology to Technology Design Migration Methodology, Impact of scaling and Design Verification using Cadence’s Custom IC tools [Design Migration methodology from 600 nm to 130 nm technology Process Design Kit (PDK), Mixed-Signal Design, Layout, Simulation, Physical Verification, Parasitic Extraction, Device Scaling, SRAM characterization]

PDK (Process Development Kits) Custom IC Design Flow Analog IC Design Frontend (Virtuoso Schematic Editor, SKILL PCell programming, ADE Explorer/Assembler, Simulation, Analysis) Analog IC Design Backend (Layout, PVS, Interpretation of DRC, ERC and LVS, Quantus Parasitic Extraction, Voltus Electromigration and IR drop analysis, Post Layout simulation) AMS Designer RTL-to-GDSII flow (verilog, VHDL, Genus synthesis, Innovus place and route, Xcelium)

PLC, Microsensor, Sensors, PCB Designing- KiCad, Quantum Computing, Electromobility, QUBO (Quadratic Unconstrained Binary Optimization), Quantum Cost Landscape, Python (Qiskit, Pandas, Numpy)

1) Worked as a Performance Engineer to analyze necessary functional bottlenecks and monitoring performance metrics in Data Science project. 2) Scripting in JavaScript and running Load Tests as a part of continuous integration process primarily to visualize key functional indicators (KPIs).

Installation and Commissioning of Ftth network for high-speed data and worked in close acquaintance with Fiber Optics.

CGPA-8.09