Vahagn Khachatryan

Teams of 4-6 people are led. A framework on top of which a few Synopsys products are developed (ICWBEV+, CATS, Yield Explorer, PWB etc.). Hierarchy traversal algorithms/libraries which allow traversal of hierarchic layout (GDSII/OASIS/etc). High performance multithreaded renderer visualizing IC layouts of tens of GB sizes. Performance analyses, optimization and multithreading of layout data readers. Support/assistance of teams building their solution on top of the Framework.

IC Yield Projection software is developed. Research and development of computational geometry algorithms for geometrical analysis/operations over arbitrary shaped polygons, (includes merging, intersecting, expanding, shrinking, critical break calculation). Research and development of algorithms analyzing/operating on complex hierarchical groups of polygons. Porting of Win32 libraries to Linux and Win64 platforms. Development of Test Chip LM (a proprietary language) to Cadence SKILL translator.

Reduced Disjunctive Normal Form (DNF) extractor for Boolean functions is developed. This was initially developed in Turbo Pascal and later was moved to C++. A program verifying a group of Boolean functions on completeness is defined and implemented.

RTP based VoIP client is implemented. Software copy protection system is developed with internet based backend verification. Small embedded programs for Atmel AVR and PIC microcontrollers are implemented. Applications for android are implemented. Check http://vahagn.dyndns.org. A multithreaded solver for Nonograms is implemented. It’s open source and can be found in http://vahagn.dyndns.org.