Zuhaib Chohan

Worked with Clock and Timing Product (CTP) Application Team. Implemented averaging algorithm using VHDL for stabilizing ADC values. Extended Master Thesis project “DDR4 Pattern Generator for Protocol Evaluation”

Working with Clock and Timing Product (CTP) Application team. Master Thesis titled "DDR4 Pattern Generator for Protocol Evaluation".

Automating Verification Environment for a Mobile SoC Platform.

Worked on project titled “Hardware based anomaly detection using NetFPGA”. Also involved in the project titled “System on a chip set top box for IPTV”.

Implemented the front-end GUI for data acquisition from acceleration sensors in MATLAB for the research project titled “Concreting Process Monitoring with Acceleration Sensors”.

Conducted lab sessions and supervised semester projects 1- Digital Logic Design 2- Embedded Systems 3- Digital Signal Processing 4- Programming Languages (C, C++, Assembly, Verilog)

Bachelor Thesis titled “Design of an adaptable system on a chip (SOC) memory controller/interface and its implementation on FPGA”.

Advanced Integrated Circuit Design, Design for Testability, Integrated Electronics Seminar, Verilog and VHDL Course and Lab, Verification Technology, Circuit Building Blocks for Communication Systems, High Speed Memory System, ASIC and FPGA Design

Electrical Circuits Course and Lab, Integrated Electronics Course and Lab, Advanced Electronics and VLSI, Communication Systems, Signal Processing, Mobile Communication, Digital Communication, Programming Skills: Verilog, C++ and Assembly