Work with Product Line Managers, silicon and hardware architects, and R&D teams to identify standardisation objectives for next-generation high-speed electrical interfaces, with emphasis on 400 Gb/s per lane and future higher-rate SERDES technologies.

Develop and regularly review Nokia standardisation strategies for chip-to-chip, chip-to-module, backplane and copper-cable electrical interfaces used in high-speed Ethernet and optical networking platforms.

Create, analyse, internally review and externally advocate technical contributions for IEEE 802.3 and OIF projects. Build technical consensus with customers, component suppliers, silicon vendors, ecosystem partners and other standards participants.

Perform link and system analysis to support standards decisions, including channel loss and reflections, insertion-loss and return-loss limits, crosstalk, jitter and noise budgets, equalisation capability, transmitter and receiver specifications, COM and other statistical or behavioural link methodologies, and interoperability trade-offs.

Evaluate modulation, baud-rate, FEC and architecture options for 400 Gb/s-per-lane and higher interfaces, considering power, latency, reach, complexity, testability, manufacturability and implementation margin.

Translate product and platform requirements into technically rigorous standards proposals, objectives, baseline text, presentations and responses to comments.

Monitor competing proposals and emerging technologies, assess their impact on Nokia product directions, and develop constructive technical alternatives when required.

Participate actively in IEEE 802.3 Working Group and task force meetings, OIF electrical and physical-layer activities, and relevant industry alliances or multi-source agreements.

Provide concise internal reports and briefings on standards progress, technical risks, decisions and implications for R&D, product management and senior leadership.

Build trusted relationships across the ecosystem and influence technical direction through credible analysis, clear communication, collaboration and negotiation.

Bachelor's degree in electrical engineering, computer engineering, applied physics or a closely related field is required; a master's degree or PhD is preferred.

Substantial hands-on experience in high-speed SERDES, electrical PHY or mixed-signal interface design, architecture, modelling, validation or product development.

Deep understanding of high-speed serial-link fundamentals, including transmitter and receiver architectures, clocking and CDR, jitter, phase noise, noise coupling, channel impairments, equalisation and link training.

Expertise with PAM4 signalling and a strong foundation in modulation, coding, BER, error distributions and the interaction between electrical link performance and FEC.

Experience with one or more high-speed interface applications such as die-to-die, chip-to-chip, chip-to-module, backplane, passive copper cable or active electrical cable links.

Working knowledge of Ethernet PHY architecture and terminology, including PCS, FEC, PMA, AUI, PMD, lane mapping and multi-lane aggregation.

Practical experience with channel and link analysis tools and methods, such as S-parameters, eye and bathtub analysis, statistical simulation, IBIS-AMI, COM, MATLAB, Python or equivalent engineering environments.

Understanding of packaging, connector, PCB, cable and module constraints at very high signalling rates, including their impact on signal integrity, power integrity and test methodology.

Experience developing specifications, compliance methods, test fixtures or interoperability plans. Familiarity with BERTs, oscilloscopes, VNAs and high-speed electrical measurements is highly desirable.

Experience participating in IEEE 802.3, OIF or another consensus-based standards organisation is strongly preferred. Demonstrated contribution authorship, technical editing or leadership is an advantage.

Excellent written and verbal communication skills, with the ability to explain complex engineering trade-offs to specialists, executives, customers and partners.

Ability to collaborate across R&D, product management, business development, technical sales and external organisations, while working effectively across time zones and organisational boundaries.

Proficiency in technical negotiation, consensus building and conflict management, with an open and respectful working style.

Strong organisational skills, autonomy and the ability to manage several fast-moving standards and technology activities in parallel.

Willingness and ability to travel internationally to standards meetings, technical workshops and industry events as required.

Key technical focus areas

400 Gb/s-per-lane and higher electrical signalling for Ethernet and optical-module interfaces.

Next-generation AUI, chip-to-module, backplane and copper-cable specifications.

PAM4, PAM6 and potential future modulation formats, equalisation architectures and link training.

Channel definition, package and board loss, crosstalk, jitter, noise, COM and interoperability methodology.

Electrical PHY power, latency, reach, testability and implementation trade-offs.

Alignment of SERDES capabilities with Ethernet PCS/FEC/PMA architecture and optical interface requirements.

What success looks like

Nokia product requirements are represented early and credibly in relevant standards projects.

Technical proposals are supported by sound analysis, clear documentation and effective coalition building.

R&D and product teams receive timely, actionable guidance on standards direction, risks and implementation implications.

Published specifications enable robust, power-efficient and interoperable high-speed interfaces aligned with industry deployment needs.

Preferred profile