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LUBIS EDA 
LUBIS EDA
LUBIS EDAhat einen Beitrag geschrieben.22. Juli 2021
We congratulate two of our founders for successfully defending their PhD thesis with outstanding results: Happy to call you Dr. Tobias Ludwig and Dr. Michael Schwarz from now on! We're lucky to have you and thank you for implementing the same motivation and outstanding work ethic within LUBIS EDA. Cheers! #lubis #leadership #motivation #founders #semiconductors
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LUBIS EDA
LUBIS EDAhat einen Beitrag geschrieben.1. Juli 2021
9 months already on our way, we took the time to do a retrospective on all the things we accomplished so far, but also what is ahead and what we can do even better! Stay tuned for what is yet to come, soon more! #lubis #correctbyconstruction #semiconductor #semiconductorindustry
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LUBIS EDA
LUBIS EDAhat einen Beitrag geschrieben.21. Mai 2021
Check out our newest teaser how our software works! Together with more information, all in our blog post: https://lubis-eda.com/4-whats-the-news-keep-up-to-date/

#4 WHAT’S THE NEWS? – KEEP UP TO DATE! - LUBIS EDA

For us it’s time to spice up our secret sauce! Improved Verification IP generation: We aim to reduce the properties to a bare minimum by removing any redundancies. On top of that we are improving the readability of our properties. New type of Verification IP: We use our new type to find multi instruction bugs in your pipelined designs.lubis-eda.com
#4 WHAT’S THE NEWS? – KEEP UP TO DATE! - LUBIS EDA
LUBIS EDA
LUBIS EDAhat einen Beitrag geschrieben.7. Mai 2021
And it goes on! Do you want to avoid re-spins and increasing costs in IC/ASIC projects by using formal methods early in the process? Check out how our Verification IP (VIP) works and how you can benefit! #lubis #eda #semiconductor #correctbyconstruction https://lubis-eda.com/how-to-avoid-re-spins-in-digital-asic-ic-projects-correct-by-construction-with-formal/

How to avoid ASIC & IC re-spins with formal verification

68% of projects require at least one re-spin. We will show you how to avoid costly re-spins in ASIC/IC projects by using formal verification early.lubis-eda.com
How to avoid ASIC & IC re-spins with formal verification
LUBIS EDA
LUBIS EDAhat einen Beitrag geschrieben.1. April 2021
We wish all of you a happy easter and wanted to take the chance to share our latest breakthroug with you! Check it out and feel free to like, share and comment. https://lubis-eda.com/blog/3-whats-the-news-keep-up-to-date/

#3 WHAT’S THE NEWS? – KEEP UP TO DATE! - LUBIS EDA

At LUBIS EDA, Summer is coming! We used the time before the easter break for a spring-clean.We worked on our code base to set our selfs up to ship new features within the next months. I guess you’re here for the new features. Let’s take a look: Full support of arrays:We extended our subset tolubis-eda.com
#3 WHAT’S THE NEWS? – KEEP UP TO DATE! - LUBIS EDA
LUBIS EDA
LUBIS EDAhat einen Beitrag geschrieben.19. März 2021
Today, formal verification is mostly used for bug hunting. Writing formal properties is time consuming and requires a certain level of expertise. The performance of formal tools increased drastically within the last decade. Trends like increasing design complexity, safety and security requirements (e.g. ISO 26262) lead to an increasing usage of formal to verify the chips. Wouldn't it be great to democratise property creation? Check out our blog post for more details: https://lubis-eda.com/blog/w ...
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LUBIS EDA
LUBIS EDAhat einen Beitrag geschrieben.9. März 2021
Today we recorded our very first podcast. Gründungsbüro TU & HS Kaiserslautern invited us to talk about the current state of our start-up, our history and future plans. The podcast will be available on all platforms in a couple of weeks. Check out www.ideenwald.org for updates on their podcast series. Thanks for inviting us! #agilehw #correctbyconstruction #ideenwald
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