AJAY MISHRA

Angestellt, ASIC/FPGA Engineer - 2A, Ciena
Bengaluru, India

Skills

FPGA Design
Field Programmable Gate Array (FPGA)
AMD FPGA
Intel FPGA
Vivado
Intel Quartus
Verilog
VHDL
RTL Design
Python
C
MatLab
Scilab
Xilinx ISE
SPI
I2C
UART
JESD
AXI
eSPI
ILA
CDC
Timing Closure
Testbench
Digital Logic Design
Perforce
Linux
Microsoft Office
Lab bringup
Electronics
DDR3
Static Timing Analysis
Chipscope Pro
SignalTap
Transceivers

Timeline

Professional experience for AJAY MISHRA

  • Current 4 years and 4 months, since Sep 2021

    ASIC/FPGA Engineer - 2A

    Ciena

    • About 6 years of semiconductor field experience in Frontend Design, right from requirements gathering to final IP delivery stage • RTL Coding/Integration skills in Verilog, VHDL • Domain knowledge/expertise in fields of FPGA/ASIC based solutions • Good debugging skills for faster error detection at early stage of designing • A good team player with quick learning capabilities

  • 1 year and 2 months, Jul 2020 - Aug 2021

    Senior Engineer-Hardware Design

    Mistral Solutions Pvt. Ltd.

  • 2 years and 10 months, Sep 2017 - Jun 2020

    Design Engineer

    Bit Mapper Integration Technologies Pvt. Ltd.

Educational background for AJAY MISHRA

  • 4 years and 2 months, May 2011 - Jun 2015

    Bachelor of Engineering (B.E.): Electronics & Communication Engineering

    Gujarat Technological University

Languages

  • English

    Fluent

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