ATTAOUI Yassine

Project: Oasys-RTL Synthesis software - Performing follow-up of non-regression tests periodically to ensure high-quality releases. - Automating test execution, analysis, and debugging to increase team productivity TCL, Bash, Csh, Python, Jenkins, Jira, SVN/Git - Debug failing tests (Timing Analysis, Place&Route, Logic Synthesis..) - Formal equivalence checking for Oasys-RTL synthesis flow safety. - Development and execution of Unit test cases to cover new functionalities.

- Implementation of Requirements Document (PLDRD) for TOP level testing & Detailed Document (PLDDD) for Module level testing. - VHDL coding of RTL TOP & MODULE level - Synthesis and Timing closure - Configuration & versioning management - Implementation of Verification Test procedure & results document (VTPR) - VHDL Coding of Test Benches & simulation using Modelsim/Questasim (Perl Scripting) - VHDL design conformity (Debug and wave analysis and Inspection) of RTL code.