Isha Gupta

• Tasked with producing timing collaterals for advanced 1.4nm (14A) test chips; executed pre- and post-layout I/O timing characterization of multi-corner, multi-voltage GPIOs using Synopsys SiliconSmart and PrimeLib, delivering liberty files for NLDM models. • Learnt about reliability and aging simulations on 14A test chips; set up custom Cadence Virtuoso testbenches across pre- and post-layout stages, incorporating basic EM/IR analysis for electrical integrity

Designed and brought up a sensor controller unit using Altium Designer, ESP32, and TMS320F2838x microcontrollers; validated hardware-software interoperability across 10+ peripheral configurations on CAN, SPI, UART, I2C, and LIN interfaces, delivering a production-ready system within a 12-month program cycle. Executed environmental testing and validation across 3 hardware builds; resolved 8+ failures identified during stress testing using 8D and root cause analysis, reducing rework cycles by ~30%.

• Tasked with improving timing for a block during clock tree synthesis; achieving 24ps positive slack on a 220ps clock period and directly reducing iteration cycles before sign-off. • Developed TCL and Python scripts to automate timing report generation and parsing critical information.