Amena Farhat
Skills
Timeline
Professional experience for Amena Farhat
- Current 4 years, since Jan 2022
DFT Engineer
Qualcomm India
ATPG SCAN insertion MBIST
- Current 4 years and 3 months, since Oct 2021
DFT ENGINEER 1
Mirafra software technologies
TRAINED IN DFT With 1.8 years of Experience DFT [design for testability] MBIST . (Synopsys SMS tetramax, VCS tool, Verdi mentor graphics) scan insertion, scan insertion with compression, boundary scan (JTAG), ATPG and MBIST Tools used: - Scan Insertion - DFT Compiler - Scan Insertion With Compression - DFT Compiler - Boundary Scan - BSD Compiler - Scan ATPG - TetraMAX - Simulation - VCS - MBIST - LV, SMS [ Implementation, verification and simulation ]
Educational background for Amena Farhat
- 2 years and 3 months, Oct 2018 - Dec 2020
VLSI design and embedded systems
Dr Ambedkar institute of technology Bangalore
- 4 years, Aug 2014 - Jul 2018
Electronics and Communication Engineering
Visvesvaraya Technological University
- 4 years and 1 month, Aug 2014 - Aug 2018
Electronics
SECAB Institute of Engineering & Technology
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