
Andyes sudirja
Fähigkeiten und Kenntnisse
Werdegang
Berufserfahrung von Andyes sudirja
- Bis heute 10 Jahre und 6 Monate, seit Dez. 2014Infineon Technologies
Senior Engineer - Test Technology Innovation (TTI)
•Developing hardware/software to overcome bottleneck process in Production Line using VB.net and C# which integrated with Microcontroller (ATMEL), FPGA and CRIO via I2C, SPI and RS232 with (firmware) Embedded C, Verilog HDL, VHDL and Labview. •PCB Design with Altium Designer 17 •Automating manual process and finding solutions to reduce human error. •Increasing accuracy of data used by Engineers/Technicians to analyze machine/line performances. • 3D Simulation factory Automation with FLEXSIM
- 4 Monate, Aug. 2014 - Nov. 2014
FPGA Engineer
PT. LEN Industri
• Developing DSP algorithm for Radar in baseband (digital) level • Designing architecture (hardware) for DSP modules in front end of Radar. • Completing the Noise Control Oscillator (NCO) module development for Radar in FPGA XILINX Kintex 7 using Verilog.
- 6 Monate, Juni 2012 - Nov. 2012
FPGA Engineer
Broadcast Microwave Services (BMS)
• Research in Single Input Single Output (SIMO) transceiver Digital Video Broadcasting – Terrestrial (DVB-T). • Developing a new algorithm of Diversity Combining for DVB-T for getting best SNR (Signal to Noise Ratio). • Creating MATLAB bit-precision model for the proposed Diversity Combining algorithm hence Telecommunication team could define the hardware performance rapidly. • Establishing hardware Diversity Combining using VHDL in FPGA Virtex V XILINX and FPGA Cyclone II ALTERA.
- 2 Jahre und 5 Monate, Apr. 2009 - Aug. 2011
Senior Digital FPGA Engineer
Fusi Global Technology
• Defining modules in Baseband Digital Video Broadcasting (DVB) • Working closely with model team (MATLAB/Telecommunication) on developing the optimum hardware performance. • Creating Digital Module for FFT-IFFT, Booth’s algorithm, Block Floating Point (BFP) arithmetic hardware, DVB-T Equalizer and FIR Filter in FPGA Xilinx and Altera using VHDL and Verilog which modelled in MATLAB. • Experience on Chip Scope-pro analyzer, Logic analyzer, AMU/Signal Generator and Osciloscope from RS.
- 1 Jahr und 1 Monat, März 2008 - März 2009
FPGA Engineer
Versatile Silicon
• Improving Digital Video Broadcasting – Terrestrial (DVB-T) and WiMax Modules to comply with DVB-H (Handheld) • Developing a new algorithm for Fast Fourier Transform for DVB-T and DVB-H. • Establishing algorithm for Fast Fourier Transform (FFT) to comply with DVB-T and DVB-H (Handheld) simultaneously. • Completing the FFT development hardware for DVB-T and DVB-H in FPGA Cyclone III. • The FFT can cover 400% FFT points with only 3% additional hardware area compared with existing FFT design.
Ausbildung von Andyes sudirja
- 1 Jahr und 3 Monate, Okt. 2011 - Dez. 2012
Microelectronics
Hochschule Darmstadt
Microelectronics Telecommunication - FPGA. My master thesis title is 'New Method of 6-Way Antenna Diversity Combining Using FPGA Altera Cyclone II EP2C5OU48L48' which used for Digital Television (DVB-T). Reasearch is located in USA-Germany company BMS (Broadcast Microwave Service) in Wiesbaden.
- 1 Jahr und 1 Monat, Okt. 2010 - Okt. 2011
Microelectronics
Bandung Institute of Technology
Microelectronics Telecommunication - FPGA. My master thesis title is 'New Method of 6-Way Antenna Diversity Combining Using FPGA Altera Cyclone II EP2C5OU48L48' which used for Digital Television (DVB-T). Reasearch is located in USA-Germany company BMS (Broadcast Microwave Service) in Wiesbaden.
- 4 Jahre und 7 Monate, Okt. 2004 - Apr. 2009
Microelectronics
Bandung Institute of Technology
FPGA Microelectroncis - Telecomunication. My final project title is "Design and Implementation 2k/4k/8k Pipeline FFT/IFFT Core for DVB-T (Digital Television) and DVB-H Using FPGA Altera Cyclone III". This project is used for Modulation module in DVB-T
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