Anusua Das

Division: Chassis and Safety (Vehicle Dynamics), Mixed Signal ASIC Development Tasks: 1. Design of RTL design of various modules for automotive brake applications 2. Testbench and support verification 3. ASIC Logic synthesis, Regression Test Analysis 4. Test shell scripting for regression testing for all modules 5. Modeling of analog block behavior for digital system verification Tools: Verilog, System Verilog, Questa-Sim, Synopsys Design Vision, Python

Topic: “CISPR25 tested adaptive LED driver with dynamic headroom control for automotive headlights” 1. Design of LED driver which is EMI qualified with adaptive headroom control which leads to better Efficiency, supports reverse battery protection and transient protection 2. system calculations and circuit simulation 3. schematic and layout 4. component assembling and general testing including EMI testing - support documentation Tools: Altium Designer, TINA-TI, LT-Spice

Topic: “Functional verification for energy efficient protocols for crossing isolation barrier” 1. Design of an universal SPI and UART interface, compatible for flexible and easy communication between an ADC and microcontroller 2. Evaluation of timing requirements and digital verification of SPI Master and Slave operation 3. Creation of bus functional models, RTL synthesis and generation of reusable IP-s for verification Tools: Verilog, NC-Sim

Topic: “Floating point to fixed point data conversion of 1-dimensional DCT Algorithm” 1. Preparation of a Simulink model of Discrete Cosine Transform (DCT) algorithm for Image compression by eliminating the problem of floating point conversion 2. Automatic conversion of code using 'fixed-point designer' toolbox and HDL coder Tools: Simulink

Topic of Research: “Synthesis of Low Power High Performance Mixed VLSI CMOS Circuits” 1. Develop new method for mixed CMOS design & performance analysis with standard CMOS logic, achieved reduced area and delay 2. Design of a clock distribution system & experimental and theoretical analysis of area, power and delay measurements of various clock distribution techniques for CMOS circuits under 130 nm tech. Tools: Cadence Virtuoso, H-Spice