Ralf Woehler

Angestellt, Manager, Research & Development FPGA, ADVA Optical Networking
Richardson, United States of America

Fähigkeiten und Kenntnisse

Team Lead (System and ASIC Engineers)
Technical Project Management
ASIC and FPGA Project Lead
Experience in international and multi-site project
US
China) -- ASIC and FPGA design experience
Hardware Description Languages "Verilog"
"System Verilog" and "VHDL" -- Verification (RTL
Gate Level)
"Open Verification Methodology" (OVM)
Digital Simulation (Verilog-XL
NC-Verilog
ModelSim
Questa
VCS)
Testbench Concepts and Implementation (Metrics and
object-oriented approaches
Regression test capabilities) -- Synthesis and Ph
Synplify
XST)
Static Timing Analysis (Primetime) -- ASIC/FPGA v
IBM
Texas Instruments
Philips
Toshiba
Xilinx -- CAD tool experience with Synopsys
Cadence
Mentor Graphics
Xilinx
Synplicity -- Telecommunication
Ethernet (10/100/1000/XGE)
SONET/SDH
Automotive
RFID transponder
Data compression and encryption (MPEG
Discrete Cosine Transformation)
Bus protocols (HDLC
PCI
ABUS
CAN
I2C
etc.)
MicroBlaze and processor sub-system implementation
RCS
CVS
ClearCase) -- C
Perl
Microsoft Office -- UNIX
Linux
Windows -- Pending patents (1. "System and Method
2. "System and Method of Defense Against Denial of

Werdegang

Berufserfahrung von Ralf Woehler

  • Current 20 years and 5 months, since Jan 2006

    Manager, Research & Development FPGA

    ADVA Optical Networking

    ASIC/FPGA Design (Component Specification, design and verification), Subproject and team lead

  • 3 years and 4 months, Oct 2002 - Jan 2006

    ASIC Engineer

    Covaro Networks (aquired by ADVA Optical Networking)

  • 1 year and 5 months, May 2001 - Sep 2002

    ASIC Engineer

    Metro-Optix

  • 3 years and 1 month, Jan 1998 - Jan 2001

    Senior ASIC Designer

    Ericsson Eurolab Deutschland

  • 1 year and 8 months, May 1996 - Dec 1997

    ASIC Design Engineer

    SICAN Braunschweig GmbH

    ASIC Designer

  • 4 years and 1 month, Mar 1992 - Mar 1996

    Contractor

    Institut fuer Angewandte Mikroelektronik GmbH

    ASIC Designer

  • 1 year and 7 months, Feb 1990 - Aug 1991

    Intern, Contractor

    Philips Semiconductors

    ASIC Design

Ausbildung von Ralf Woehler

  • 1991 - 1996

    Electrical Engineering

    Technische Universitaet Carolo-Wilhelmina zu Braunschweig

  • 1987 - 1991

    Electrical Engineering

    Fachhochschule Luebeck

Sprachen

  • German

    C2 (Verhandlungssicher / Muttersprachlich)

  • English

    C1 (Fließend)

  • French

    A1-A2 (Grundkenntnisse)

  • Italian

    A1-A2 (Grundkenntnisse)

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