Avdhesh Sharma

Designing a new MAC layer protocol for Wireless Sensor Networks.

Designed hardware for two robots to automate a clinical process. Designed software to control the robots to automate a clinical process. Acquired proficiency in MATLAB and LabView.

- Designed Cache Coherency Protocol for Time Triggered Network on Chip. - Acquired proficiency in SystemC and Time Triggered Networks.

-- Development and implementation of Verification Environment from scratch, Active/Passive UVCs and test cases in SystemVerilog based on the cutting-edge UVM and OVM methodology. -- RTL Code debugging and fixing. -- Expertise in Functional Verification, BFM Design and Code & Functional Coverage. -- Designed AHB Arbiter and Assertion Checker -- Debugging and code optimization for AXI master. -- Successful tape-out of Qualcomm’s SoC.

** 2011 | AMBA AHB VIP development -- Worked on AHB VIP code optimization for maximum performance and achieving 100% code coverage and functional coverage. -- Developed IP Verification suite for AHB/APB using OVM methodology and Verilog. ** 2010 | SATA VIP development -- Verification of the Transport Layer of SATA VIP. -- Worked on SATA with LSI and SanDisk and developed PHY layer in the VIP with Verilog.

Developed software module for V-SAT in JAVA.

Developed Software module for V-SAT in JAVA.

Material Science; Machine Elements; Automation & Industrial Communication; Project Management; Engineering Design; Machine Dynamics & Systems Dynamics; Sensorics; Actorics; Modelling and Simulation; Software Engineering; Mechatronics Systems; Fluid Power; Advanced Control

Electronics, Embedded Systems, Economics, Business Management, Communication Systems, Device Fabrication, Electrical Engineering