Bairesha Kaadsiddara Ramesh

Experienced in the design of Sampler and Sub ADC blocks in a high-speed networking product, including feasibility study, design, simulations, floor planning, layout, power grid alignment, routing, DRC/DFM/LVS and EMIR analysis. – Professional exposure for complete IP development cycle. – Exposure to 180nm, 90nm, 28nm and 16nm technology nodes. – Good understanding of ADC architectures and the building blocks of High speed ADC.

Involved in High Temperature Operating Life Testing (HTOL) for PMIC (Power management Integrated Circuit) and Audio Codec ICs. Involved in building GUI for the HTOL process tool using Python QT. Worked on adding features to core software. Worked on Python unit testing by using Pytest, Tox and Jenkins.

I was involved in integrating the data fixing codes and improving the service to facilitate the business that is being carried out in central European countries. Involved in designing, creating, maintaining several database effectively also involved in different design change and architectural change by working closely with the architects.

BHEL, government organization in India offers a wide range of state-of-art Solar Photo Voltaic Modules, Capacitors, PCB etc. I was trained in assembling and testing the Printed circuit boards, firmware development for testing of photo voltaic cells manufactured by BHEL and analyse the results.

Circuit Building Blocks for Power Systems,Verilog & VHDL,Advanced Digital Integrated Circuit Design (CADENCE),VHDL Lab, Advanced Digital Integrated Circuit Design Lab, High Level Synthesis, Printed Electronics, Microprocessor Systems, Project Seminar DFT,DSP,Mobile Networking, Computer Networks.

Electronics, Verilog, VHDL, FPGA, VLSI, Embedded systems,Hardware design, analog design, digital design, signal processing, communications, signal processing, Information theory Circuit designing, telecommunications, antennas etc