Damien Pretet

I participated to the development of an IDE assisting IP developers to integrate their processing into FPGA powered cloud like Amazon AWS F1. I was the principal designer who developed the FPGA design skeleton and participated to the architecture definition, heavily relying on AMBA 4 Specification (AXI4/AXI4-Stream/AXI4-lite). I developed many python tools around this flow and put in place with my team a strong continuous delivery pipeline.

I joined PLDA to contribute to their PCIe IP controller. This IP targets as well ASIC or Xilinx/Altera FPGAs. I developed the reference design, participated to the formal verification with Spyglass and put in place a system to demonstrate virtualization capability of PLDA IP (PCIe SR-IOV).

As principal engineer, I was in charge to study Hard Disk Drive PRML system. PRML (Partial Response Maximum Likelihood) is a data channel architecture retrieving data from the signal sampled on magnetic plates of the HDD. I implemented in a Xilinx Virtex 5 FPGA a generic channel able to process any HDD (vendor and generation. I also put in place a full validation flow, relying on C++ simulation, VHDL simulation and hardware validation. I also did TI DSP programming to control the HDD actuators.

Communication & Systems - Digital Signal Processing

Electronic Curriculum