Dmitry Kopotev

- Completion of 6 flash memory microcontroller projects at 65nm and 40nm - Supporting close collaboration with back-end partner Racyics GmbH - SDC timing constraints development for both functional and test modes - Constraining ONFI flash and host interfaces for speeds up to 800 Mbps - Static Timing Analysis (STA) and timing closure with Synopsys PrimeTime - RTL linting, CDC, and RDC checks using Synopsys SpyGlass - Design analysis for multicycle paths - Clock and reset trees optimization

Received a job offer in February 2014 and signed a contract to begin on the 1st of July 2014. Due to a pending US export license, I could not start as scheduled. After several months of waiting for the license to arrive and running low on savings, in September 2014 I decided to pursue another opportunity at Hyperstone. The license was ultimately approved shortly after I had committed to the new role.

Brought in by Cadence to support the quality of Cadence Physical Verification System (DRC, LVS, ERC) and Cadence Virtuoso (also IPVS). The role involved: - Running and analyzing regression test cases - Creating test cases for assigned requests (bugs and enhancements) - Reviewing functional specifications, creating test specifications, analyzing requirements, and providing feedback - Writing scripts (Perl, shell)

My main area of responsibility was static timing analysis, including: - Building the static timing model for the top level of chip design - Debugging time delays at the top level - Creating timing constraints for individual blocks - Developing and enhancing an automated algorithm for constraint generation - Physical design (RTL to GDSII)

Foreign languages department (evening classes). Qualification: Translator in the field of professional communication.

Micro- and nanoelectronics department. Term papers: Design of integrated circuits, passed. Practical work: Graduation practical work, 20 weeks, excellent. Final state examinations: Interdisciplinary examination on speciality, excellent. Realization and presentation of final expert paper on the subject of "Static Timing Analysis flow and microprocessor's blocks budgeting for 65 nm node", 16 weeks, excellent.