Gilberto Rodrigues

Development of a generic Memory Mapped JTAG Interface with chain SerDes in VHDL to access any Processors Boundary Scan Cells. Hardware testing using ModelSim. Integration of the hardware developed with the MCTRL IO port of the uP LEON3. Co-Development of a Driver for the JTAG interface and userspace application. The software runs in the FPGA and is controlled by a host through TCP/IP.

During my internship I developed a hardware interface to access the chains of Boundary Scan of uP ERC32 by JTAG, using VHDL programming language; all the modules developed were simulated in ModelSim. This interface was integrated in the uP LEON3 through the memory controller I/O port. To control the developed interface, I participated in the programming of a driver and an application which run on SO Linux for Snapgear Embedded Systems.