Keyvan Shahin

• Conducting research in FPGA‑based computing, configurable hardware architectures, digital signal processing, and hardware/software co‑design. • Designed and developed HADES, a reusable FPGA‑based framework for hardware‑accelerated bit‑true fixed‑point simulation and automated bit‑width optimization, including runtime‑configurable arithmetic and a dual‑instance Golden‑versus‑DUT evaluation architecture. • Implemented HADES in VHDL at the RTL level and C++ with Vitis HLS, developing width‑configurable ari

• Developed and optimized a Virtual Coarse‑Grained Reconfigurable Array (VCGRA) in VHDL for a reconfigurable high‑performance computing platform, including processing elements, interconnect architectures, and FPGA implementation. • Designedand implemented the VCGRA interface to the ARM‑basedprocessing systemonXilinx Zynq, replacing the orig‑inal communication bottleneck with AXI‑Stream interfaces for input and output and simplifying software integration and benchmarking. • Designed FPGA‑based sensor‑fusio

• Worked on digital hardware for MAPCS, a Distributed Control System (DCS) developed for industrial power‑plant applications; the first system release was deployed at power plants in Iraq. • Contributed to the architecture and technology definition of the second‑generationMAPCSplatform, evaluating digital I/O architectures, hardware platforms, communication protocols, and relevant standards. • Implemented and evaluated a CAN‑FD communication stack as part of the technology development for the next‑generat

• Designedand implementedFPGA‑baseddigital hardware for radar, identification, radio‑positioning, andsignal‑detection systems, primarily using VHDL on Xilinx Spartan and Virtex devices. • Developed FPGA control and interface logic for PLLs, ADCs, DACs, clocking devices, attenuators, and other RF compo‑nents, including device‑specific communication protocols and control functions. • Designed PC‑to‑FPGA control interfaces and C++/MFC applications for configuring and operating FPGA and RF‑board functionality

• Designed and implemented LDPC forward‑error‑correction algorithms in MATLAB and FPGA hardware.

• Translated and summarized academic material for internal publications.

• Thesis: Design and FPGA implementation of a real-time 2x2 MIMO wireless channel emulator based on SCM (Spatial Channel Model). • Designed an ASIC prototype of a Gaussian Variate Generator in 0.18 μmTSMC technology. • Total Grade: 16.47 / 20; Thesis Grade: 19 / 20