Manideep Kalava

Angestellt, Master Thesis | Hardware Emulation for IP level Verification, Infineon Technologies

Fähigkeiten und Kenntnisse

MatLab
Python
Java
Agile
Git
Jenkins
Behavior Driven Development
LTspice
C
Simulink
Team work
Flexibility
Reliability
Verilog VHDL
SystemVerilog
UVM
SystemC
Linux
Formal Verification
Functional Verification
Digital Functional verification
Hardware emulation
Constrained Random Verification
Assertion based verification
UML architecture
RTL simulation
Simulation
RISC-V Assembly language
MS Office
attention to detail
willingness to learn
punctual
Commitment
Fast learner
Organizational skills
open minded
Problem Solving
ability to work under pressure
Technical Knowledge

Werdegang

Berufserfahrung von Manideep Kalava

  • Bis heute 5 Monate, seit Aug. 2025

    Master Thesis | Hardware Emulation for IP level Verification

    Infineon Technologies

    Created a SystemVerilog UVM hardware emulation ( Palladium Z2) testbench for IP-level verification of the complex RTL of an in-house Timer Counter Pulse Width Modulation (TCPWM) design Integrated AHB Accelerated Verification IP (AHB AVIP) provides a connection to the DUT in the emulation, while the master agent of the testbench remains in simulation(Xcelium) formaximum visibility of internal signals The pairwise testing technique is employed to generate the configurations of input parameters

  • 9 Monate, Nov. 2024 - Juli 2025

    Working Student

    Infineon Technologies

    (DLTs) used in production testing of firmware of NVM flash memory models, ensuring accurate register model checks and NVM model manipulation Utilized SystemVerilog, UVM methodology, Cadence Xcelium, and Indago to perform digital functional verification and debug complex hardware simulations cross-collaboration with different teams while interpreting specifications from Enterprise Architect (UML) to create reliable verification test cases, improving DLT reliability

  • 5 Monate, Juni 2024 - Okt. 2024

    Intern

    Infineon Technologies

    Development of Formal Verification methodology for Firmware drivers verification and Hypervisors using Bounded Model Checker for C and C++ (CBMC) for an Automotive microcontroller Developed and managed Python scripts and Makefiles to automate processes and streamline workflows, resulting in increased efficiency, productivity, and code quality Achieved a significant 50% increase in code coverage metrics, ensuring more comprehensive testing and validation of code

  • 7 Monate, Nov. 2023 - Mai 2024

    Working Student

    TU Chemnitz

    Developed expertise in programming control software using NI LABVIEW for Precision Electro-Chemical (PECM) machining applications Interacted with various tools, including DAQ devices, Source generators, Multimeters, and NI MID-7604 stepper motor drives, to control and precision-engineer axis movements

  • 1 Jahr und 2 Monate, Aug. 2021 - Sep. 2022

    Test Engineer

    Infosys Ltd

    Automated testing workflows using Behavior Driven Development principles (Selenium + Cucumber) achieving a 98% regression pass rate on production environments Executed functional tests using Jenkins on BrowserStack for production web applications

Ausbildung von Manideep Kalava

  • Bis heute 3 Jahre und 3 Monate, seit Okt. 2022

    Embedded Systems

    TU Chemnitz

    Coursework: Design & Verification of Digital Systems | Hardware/ Software-Codesign | Real-time Systems | Advanced Platforms for Automotive Systems | Digital Components & Architecture

  • 4 Jahre, Juli 2017 - Juni 2021

    Electrical and Electronics Engineering

    Vellore Institute of Technology (VIT)

    Final CGPA: 1.9 (German Scale) Focus: Semiconductor technology | Network and control Theory | Digital and Analog devices | Troubleshooting | Programming (OOPS) | micro-controllers & processors

Sprachen

  • Englisch

    Fließend

  • Deutsch

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