Marcel Favini

In the scope of developing a crypto-coprocessor board, I contributed to the appropriate DDR2 memory controller of the board by evaluating the existing implementation of the memory controller. Based on these studies I implemented a functionally enhanced version of a multiport DDR2 memory controller in a field programmable gate array (FPGA). I completed this work by simulating the new design with bus functional models which demonstrated that my method and implementation fulfilled the requirements

Implementation and extension of a demonstration application for a sophisticated low power ultra-wide-band wireless modem using Matlab and state of the art measurement equipment

Support of master courses in technology and innovation management headed by Prof. Dr. Roman Boutellier; support of the publication activities of the chair through literature research; creation and design of slides, graphs and tables in MS PowerPoint and MS Excel, digitalization and administration of literature by using a reference database; support in organization of team activities and events; homepage (CMS) administration

Exchange Student; Subjects: Mobile Communication Systems, Medical Imaging (MRI), Intelligent Image Processing

Digital Chip Design, Signal Processing