Marieta Kanovska

Precise layout techniques with good symmetry, optimized rooting of blocks regarding induced parasitics, critical in High speed designs; careful EM prevention techniques regarding high currents; TSMC nanometer technologies; good knowledge and application of fab recommendations, DFM; Mentor Caliber Physical verification tools

Verifying construction and connectivity of IC layout design databases Activities oriented to achieve accuracy and improvement of layout database Comparing the LPE results with three-dimensional solver, Synopsys Validation of Updates – technological, Used software, applied Tech files DRC, LVS, ERC, LPE; Cadence, Mentor, Synopsys Physical verification software; bulk CMOS, SOI; Standard and RF technologies

Development of CMOS design kits for Silway technologies Standard library cells description for P&R Design and layout of standard analog cells, I/O buffers, ESD protections, library included; analog blocks for ASIC projects Full custom layout, DRC, LVS Catena layout tools, Very Best Simulation Environment, Windows NT

ASIC Sensor based layout – Consumer, Automotive applications Custom Mixed signal, Analog blocks IC layout, Relevant layout techniques Evaluation of technical issues in IC layout, applying constraints derived from test chips, consideration of technology required layout techniques for bringing the layout parameters close to these intended by the schematics. X-fab technologies, ICED layout tool, Cadence Virtuoso, Dracula, Unix