Mario Di Ronza

Bis 2019, Project Lead, Intel Deutschland GmbH
Munich, Germany

Fähigkeiten und Kenntnisse

Engineering services in fields of digital IC and c
project- and product management

Werdegang

Berufserfahrung von Mario Di Ronza

  • Current 6 years and 6 months, since Dec 2019

    IP Logic Design Engineer

    Apple Mobile B.V. & Co. KG

  • Current 15 years and 11 months, since Jul 2010

    Freelance

    Self-employed

    Engineering services in fields of digital IC and circuit development, semiconductor memory testing, project- and product management, product qualification, software programming, application development for embedded systems, computer and building automation networks.

  • 2 years and 10 months, Feb 2017 - Nov 2019

    Project Lead

    Intel Deutschland GmbH

    Digital design and verification lead.

  • 8 years and 10 months, Feb 2011 - Nov 2019

    Digital Design Engineer

    Intel Mobile Communications GmbH

  • 8 months, Oct 2009 - May 2010

    Sales assistant

    Qeron Technology GmbH & Co. KG, Starnberg, Germany

  • 2 years and 10 months, Mar 2006 - Dec 2008

    Senior Manager Roadmap Management.

    QIMONDA AG, Gustav-Heinemann-Ring 212, D-81739 Munich, Germany

    DRAM competitive analysis. Support to strategy and business development. Product roadmap management and publishing company wide. Development and maintenance of roadmap management tools.

  • 5 years and 10 months, May 2000 - Feb 2006

    Staff Engineer SRAM/ROM development.

    INFINEON TECHNOLOGIES AG, Balanstr.73, D-81541 Munich, Germany

    Design of user-configurable fault-tolerant architectures for embedded 6T SRAM (6-Transistor Static Random Access Memory) arrays. Development of driving logic for OTP (One-Time Programmable) metal and poly fuses. Digital macrocell modeling (VHDL/Verilog). Development of HDL code generators (VHDL/Verilog). Expert support for large-volume designs. Technical documentation.

  • 1 year and 9 months, Sep 1998 - May 2000

    ASIC development engineer.

    IPM Group, PO.BOX 152, I-80022 Arzano NA, Italy

    FPGA and ASIC development engineer.

  • 7 years and 2 months, Jul 1991 - Aug 1998

    Digital/analog circuit design engineer – Wireline communication.

    IPM Group, PO.BOX 152, I-80022 Arzano NA, Italy

    Design of systems and terminals for public telephony. Digital and analog circuit design, including thick-film analog circuits. Product qualification at the accredited laboratories, including physical layer and EMC (Electro-Magnetic Compatibility) tests. Design specification and project management.

Ausbildung von Mario Di Ronza

  • 8 years and 10 months, Oct 1982 - Jul 1991

    Electronic Engineering

    Universita´ degli Studi Federico II, Naples, Italy

    Biomedics

Sprachen

  • German

    B1-B2 (Gute Kenntnisse)

  • English

    C1 (Fließend)

  • Italian

    C2 (Verhandlungssicher / Muttersprachlich)

  • French

    A1-A2 (Grundkenntnisse)

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