Matthew Cappello

Senior FPGA Design and Verification Engineer
Full-time employee in Munich
Munich
Munich
Aerospace
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Matthew Cappello's haves

  • C++
  • Microsemi Libero SoC
  • Network Analyzer
  • Altera Quartus
  • Oscilloscope
  • MATLAB
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Matthew Cappello's professional experience

1 year
9 months
05/2018 - to present
Senior FPGA Design and Verification Engineer
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Senior Engineer
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3 years
10/2012 - 09/2015
Engineer II
General Dynamics Electric Boat
5 months
11/2011 - 03/2012
Teaching Assistant
Engineer Co-op
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Engineer Co-op
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Matthew Cappello's educational background

  • 09/2007 - 05/2012
    Rochester Institute of Technology
    Master of Science (MSc), Electrical Engineering, GPA 3.88/4.00
    Focus Area: Control Systems; Thesis - "A Model Order Reduction Method for Lightly Damped State Space Systems" - Used MATLAB to create computationally efficient model order reduction method for both continuous and discrete time SISO and MIMO systems based on modal-canonic form of state space model.
  • 09/2007 - 05/2012
    Rochester Institute of Technology
    Bachelor of Science (BSc), Electrical Engineering, GPA 3.69/4.00
    Mathematics Minor; Senior Design Project-Worked with multidisciplinary team to condition power generated by wind turbine to fast and trickle charge NiMH battery packs. Generated schematic with Orcad, chose components, prototyped hardware on a breadboard; Honors Engineering Program; Tau Beta Pi

Matthew Cappello speaks the following languages:

  • English (First language)
  • German (Basic knowledge)
  • Spanish (Basic knowledge)

Matthew Cappello's interests

  • Home Project: LED Sunrise Alarm Clock
  • Home Project: Wireless Smart Thermostat with Web Interface
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