Mayank Pedhadiya

Experienced in RTL design and verification, specializing in Verilog/VHDL for CPUs, memory controllers, and communication interfaces. Skilled in testbench development, debugging, waveform analysis, static timing analysis (STA), and functional verification using ModelSim, Xilinx Vivado, and UVM. Proficient in EDA tools, synthesis, and FPGA prototyping for digital circuit optimization.

As an Embedded Software Intern, responsibilities include developing and debugging firmware for microcontrollers, CPUs, and SoCs using C/C++. Tasks involve device driver development, RTOS interaction, and implementing communication protocols (UART, I2C, SPI, Ethernet). Interns also optimize memory/power usage and test embedded systems using oscilloscopes, debuggers, and logic analyzers.

Grade: 2.2 Relevant subjects Final Project: Three tank control systems using MATLAB Real-Time S/w Development System On Chip Design Digital Design with VHDL(FPGA) Medical Systems (DSP) Industrial Systems Discrete Control Systems

Relevant subjects Computer Programming Utilization, Control System Engineering Digital Electronic, Digital Communication, Digital Signal Processing, Wireless Communication System Electronic Drives and Circuit, Circuit Network, Analog circuit Design Micro Processor & microcontroller and Interfacing Signal System, VLSI Technology and Design Data Communication & Networking