Dr. Matthias Gries

Munich Research Center (MRC) -- Advanced Computing R&D: Application-driven codesign of memory, compute and interconnect for Arm AArch64 platform SoCs (System-on-Chip) with focus on servers, data centers and scientific computing/HPC software enabling.

technical lead: Design methods, hardware & software technologies for memory subsystems and energy efficient multicore platforms. - Non-Volatile Memory (PCM, STT) integration into memory & storage hierarchy - Manycore CPU SCC (Single-chip Cloud Computer) DDR3 subsystem design - Predictive methods for application-driven resource management (thermal & power control [DVFS])

Implemented thin system SW layer (C/C++) w/ min. mem footprint for proprietary network processor, prototyped bus control on FPGA for MP-SoC (OCP on-chip communication, ethernet, IPv4 forwarding), concept engineering of DSLAM network processor & WLAN IEEE 802.11n access point processor (AMBA, OCP, CoreConnect, PCIe, MIPS core IP, IEEE 802.3).

Developed automation tools for designing application-specific instruction-set processors, evaluated architectures and programming models for network processors.

Teaching assistant for classes on hardware-software codesign, computer architecture, computer networks, operating systems, and embedded systems' design.

network processing, Quality of Service, active queue management, real-time scheduling

digital signal processing, image processing, computer architecture, filter design