Neeraj Sanjay Mogal

Full-time roles in power electronics or test. Available now, open to relocate

Bis 2025, Master Thesis – LVDC Fault Detection & ML-based Protection, Fachgebiet Mechatronik und Elektrische Antriebssysteme (MEAS)
Bis 2025, Commercial Vehicle Technology, Technische Universität Kaiserslautern
Kaiserslautern, Deutschland

Fähigkeiten und Kenntnisse

Power electronics
MatLab/Simulink
Machine Learning
MS Office
German
English Language
LVDC Microgrids
Electromobility
Steer-by-Wire
Electromechanical Actuators
EV/HEV Systems
C++
LabVIEW
Wavelet analysis
Random Forest
Support Vector Machine (SVM)
Digital Signal Processing
scikit-learn
Raspberry Pi projects
Arduino Uno
Real-Time Systems
ANSYS Maxwell
Autodesk Fusion 360
Digital Twin
Requirements Engineering
CAN Bus
Management
C# Programmierung
Communication skills
Team work
independent
Analytical skills
Confidentiality
willingness to learn
Motivation
Negotiation skills
problem solving skills
ability to work under pressure
Fast learner
Electromagnetic FEM (ANSYS Maxwell)
Requirements verification
Python
C programming
Eagle (PCB design)
Catia V5
PTC Creo Parametric
Git
Artificial intelligence
Fault
Applied Physics
Microsoft Word
Embedded Systems
AutoCAD
Electrical Engineering
Automotive engineering
Software Development
Mechatronics
MatLab
Application
Engineering
Cost estimation
CATIA
CAD
PowerPoint
SolidWorks
PTC Creo
Presentation skills
ambitious
punctual
Reliability
Problem Solving
Friendliness
thoughtful
Responsible
attention to detail
Patience
willingness to travel
self-confidence
Curiosity
International experience
Technical Knowledge

Werdegang

Berufserfahrung von Neeraj Sanjay Mogal

  • 3 Monate, Jan. 2026 - März 2026

    Research Affiliate (Independent), Power Systems

    Independent research (PCIM Europe 2026 paper)

    Extended my master's research into a peer-reviewed paper published at PCIM Europe 2026: refined the simulation models and wrote the technical documentation with three co-authors. Studied power-system and grid-protection fundamentals on my own, including HVDC protection.

  • 6 Monate, Mai 2025 - Okt. 2025

    Master Thesis – LVDC Fault Detection & ML-based Protection

    Fachgebiet Mechatronik und Elektrische Antriebssysteme (MEAS)

    Developed an embedded-ready fault detection and isolation system for DC microgrids as part of M.Sc. thesis research. Applied physics-guided machine learning to achieve real-time fault classification with high accuracy and low inference latency. Findings accepted for presentation at PCIM Europe 2026.

  • 9 Monate, Dez. 2024 - Aug. 2025

    Student Assistant – Virtual Product Development

    Lehrstuhl für Virtuelle Produktentwicklung (VPE) , RPTU Kaiserslautern-Landau

    Built CAD models in Fusion 360, integrated into Unity and programmed in C# for VR engineering applications. Developed Raspberry Pi-controlled smart-home devices for STEM education.

  • 8 Monate, Mai 2024 - Dez. 2024

    Studentische Hilfskraft

    MEGT - Fachbereich Maschinenbau und Verfahrenstechnik (RPTU)

    Analysed lubricating-grease bleeding measurements using LabVIEW. Processed viscometer datasets with MATLAB for tribological characterisation.

  • 6 Monate, Apr. 2023 - Sep. 2023

    Engineering Intern – Electromechanical Actuator Development

    ZF Group

    Drove the end-to-end development of steer-by-wire systems by engineering and validating electromechanical actuators and digital twins (ANSYS, MATLAB/Simulink), complemented by targeted technology screening and detailed stakeholder reporting.

  • 1 Jahr, Juli 2020 - Juni 2021

    Business Operations Intern

    Booster Plant Genetics Pvt. Ltd.

  • 4 Monate, Mai 2019 - Aug. 2019

    Design & Engineering Intern

    VDL Pinnacle Enginnering India

    Engineering calculations, design drawings and cost estimates for jigs and fixtures using CREO and CATIA.

Ausbildung von Neeraj Sanjay Mogal

  • 4 Jahre und 2 Monate, Okt. 2021 - Nov. 2025

    Commercial Vehicle Technology

    Technische Universität Kaiserslautern

    Power electronics, embedded systems, EV/HEV requirements engineering, electromobility, CAN bus simulation. Thesis: Fault detection and isolation in meshed LVDC microgrids using ML pipeline

  • 4 Jahre und 3 Monate, Juni 2016 - Aug. 2020

    Mechatronics Engineering

    Ajeenkya DY Patil Universoty , Pune

    Analog & digital electronics, microcontrollers, control systems, signal processing, MATLAB. CGPA: 8.09/10 — First Class with Honours.

Sprachen

  • Deutsch

    B1-B2 (Gute Kenntnisse)

  • Englisch

    C1 (Fließend)

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