Paul Jarmola

Angestellt, Software Project Manager, Continental Teves AG & Co. oHG, Frankfurt am Main
Frankfurt am Main, Germany

Fähigkeiten und Kenntnisse

Project Management
Technical Team Lead
FPGA
Embedded
FAE - Technical Sales
Team Management
Xilinx
Lattice
C++
Microcontroller
Altera
Patent Registration
RTL Simulation
Pilot's Licence
Softwareentwicklung

Werdegang

Berufserfahrung von Paul Jarmola

  • Current 6 years and 5 months, since Jan 2020

    Software Project Manager

    Continental Teves AG & Co. oHG, Frankfurt am Main

  • 1 year and 2 months, Nov 2018 - Dec 2019

    Software Projektmanager

    WEBER GmbH - Technik pur
  • 7 months, Apr 2018 - Oct 2018

    Director Product Development PikeOS

    SYSGO AG

  • 1 year and 5 months, Apr 2016 - Aug 2017

    Technical Lead Embedded Systems

    Panasonic Automotive & Industrial Systems Europe GmbH

    Project Management Deep Level of Algo/HW/SW/Embedded Understanding Needed Communication Oriented Created Work Packages for External Companies/Contractors Contact to chip companies Involved in Job Interview Process Task at Hand: Automotive Process Orientation Port PC C/C++ Algorithm Code to Embedded Platforms Parallel Image Processing of Optical Flow Algorithms on both ARM and FPGA

  • 3 years and 1 month, Mar 2013 - Mar 2016

    SFAE - Altera FPGAs

    Arrow Central Europe GmbH

    As a dedicated FAE (dFAE) for Altera FPGA/CPLD products, I am responsible for maintaining customers interest, projects as well as future development plans all enclosed within the scope of the logistics business at Arrow Electronics.

  • 3 years and 7 months, Jul 2009 - Jan 2013

    FPGA Hardware Development Engineer

    Magna Electronics Europe GmbH & Co

    Design FPGAs consisting of: -AXI Interfaces -SPI BUS -I2C BUS -BT656 Video Format -DDR3 Controllers -LVDS CameraLink -UART -Colour Space Conversion -Algorithm Design Creation and maintenance of simulation testbenches Commissioning of hardware interfaces Verification of PCB designs Development tool experience in: -ModelSim -ISE (Xilinx) -EDK -ispLever (Lattice)

  • 1 year and 10 months, Oct 2006 - Jul 2008

    FPGA Hardware Design Engineer

    Ulm University

    -hired externally by Daimler AG to develop a bird's-eye-view system using FPGAs -successfully developed multi-camera processing algorithms using VHDL -realized park assistance algorithms for FPGA -supervised students contributing towards the project

Ausbildung von Paul Jarmola

  • 2 years and 4 months, Apr 2004 - Jul 2006

    Communications Technology (Electrical Engineering)

    Ulm University

    Microelectronics, VHDL/FPGA Embedded Hardware Design

  • 5 years and 8 months, Sep 1998 - Apr 2004

    Computer Science

    University of Western Ontario

  • 5 years and 8 months, Sep 1998 - Apr 2004

    Electrical Engineering

    University of Western Ontario

    Electrical Engineering

Sprachen

  • English

    C2 (Verhandlungssicher / Muttersprachlich)

  • German

    C1 (Fließend)

  • Polish

    C1 (Fließend)

  • French

    B1-B2 (Gute Kenntnisse)

  • Ukrainian First Language

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