Pavan Prakash

Layout design of a full rate clock and data recovery DLL at 6.666Gbps in TSMC 65nm CMOS technology. Sign off steps for TSMC tape-out (Dated: 22.11.2017) with global DRC, LVS, IR Drop Analysis, Parasitic extraction, filler generation and GDS file import and export file generation. Tools: Virtuoso Layout/XL, Cadence Virtuoso, Calibre verification tools, Assura verification tools

"Design of a Clock and Data Recovery Delay Locked Loop at 6.666Gbps in 65nm CMOS Technology" . Tasks: Schematic design and implementation Noise and Jitter Analysis System model in simulink Tools: Cadence Virtuoso, MATLAB Simulink

Projects worked: 1. Bombardier Fly by Wire Power Converter 2. Embraer Legacy System Digital Generator Control Unit Project Responsibilities: 1. Requirement Analysis: Analysing Requirements and breaking it down for implementation 2. Embedded Design: High level and detailed level designing 3. Implementation: Programming the Hardware with the code to check system functionality 4. Maintenance: Analysing and fixing defects if any Tools: Tanner EDA, SCADE, Understand C++, Green Hills MULTI IDE

Worked on Project titled "Data Acquisition Software for Testing Upper Control System of Light Combat Helicopter Using LabVIEW" Responsibilities: LabVIEW code for data acquisition and Design of Transducers for signal acquisition Tools: LabVIEW

Circuit and Systems Design, Fast Integrated Circuits for Digital Communications, Integrated Circuits for Wireless Communication, Fields and Waves, Advanced System Theory, Introduction to Algorithms, Modeling and Simulation, Robotics, Solar Electric and Energy Systems

Analog and Digital Communication, Wireless Communication, Optical Fiber Communication, Analog Electronic Circuits, Digital Signal Processing, Signals and Systems, Information Theory and Coding, Logic Design, Network Analysis, Embedded Systems.