Ing. Swaroop Badekara

Design of High performance ADC for CMOS image sensors.

– The full delta sigma design includes DS modulator and Sinc2 decimation filter. – Design of switched capacitors, OTA, high speed clocked comparators, D-flip flops, adders, averagers, hold registers etc., – Non-ideal effects have been investigated in accordance with different feedback topology an their impact quantified. – Performing Montecarlo/corner simulations for further analysis.

The main objective of the task was to design a 2 MHz bandwidth, K-path deltasigma (KD1S) converter with 6-bit ENOB. – New concept of sharing the op-amp across K-paths to realize a (KD1S) topology.

– Worked on Creating an approach/concept to a software solution to enable a software controlled reliability test of RF MEMS switches. – Designing test setups for component level measurements, switching parameters, lifetime calculations, contact resistance degradation etc.

Micro-system Design, Advance Integrated Circuit Technology, CMOS VLSI Design, Micro and Nano Devices and Reliability Engineering.

CMOS VLSI, Analog and Mixed Mode VLSI Design, Linear IC’s, Analog Electronic Circuits, Digital signal processing and Signals & Systems