Sergey Dubinin

Development and implementation of part of Verification Environment from scratch, Active/Passive UVCs and test cases in SystemVerilog based on cutting-edge UVM methodology

[*] Implementation of part of verification environment and tests for FPGA image processing project in SystemVerilog (UVM). [*] RTL code debug and fix. [*] Found and fixed bugs in Mobile DDR memory model (Micron IP), that was generated inside MIG controller IP by Xilinx CORE Generator tool.

[*] Implementation of part of high-speed (500MHz) FPGA asynchronous project (Xilinx/Virtex-6). [*] Writing Top-Level Spec. [*] Support with solving verification environment problems and integration with verification team.

Implementing complete and universal work-around driver for DDR3 controller (DesignWare/Synopsys) integrated as IP in ASIC. The driver was implemented to support all available working modes (800 / 1066 / 1333 MT/s). Implementation included as well tight work with Synopsys validation team locally (at Canada branch).

[*] RTL design and verification of FIR filter following pipeline architecture including rounding and saturation. [*] Implementing automatic verification environment to check proper connectivity of different SRAMs/DPRAMs integrated in ASIC (over 50 different kinds). [**] Received an award letter and bonus for outstanding performance. P.S. I finished to work for the company due to LOCAL OFFICE SHUT DOWN of whole Israeli branch.

Implementing FROM SCRATCH: [FPGA]: DMA Controller – [Altera/Cyclone]. [ASIC]: Communication Controller based on RS232 (multi-asynchronous clock design). Both 2 projects were implemented by covering all Front-End R&D stages (MRD -> Netlist) as follows: writing Top-Level Spec, Micro-architecture development, RTL coding, writing Verification Plan document, implementing self-checking Verification Environment, running Simulations (Functional + GLS), Synthesis, STA.

[*] FPGA design from a scratch - AFCI (Arc Fault Circuit Interrupter) [*] Participation in development of test equipment machines (JIGs) and making HW circuit prototypes for further integration to final product [*] System integration [*] Customer support / presentation of the system abroad [*] PCB cards testing / fixing circuit malfunctions (at all levels of difficulty). Tight work with oscilloscopes, power calibrators, DVMs, electrical circuit sheets, etc...

Intensive professional course from Cadence - SVA (SystemVerilog Assertions) + introduction to Formal Verification. Course included theoretical part and practical implementation (labs). Took place in Cadence Training Center / Munich.

Intensive professional course from Cadence - Digital Verification with SystemVerilog using UVM methodology + RegModel creation and usage. Created from scratch UVM environment (including active UVCs, checkers, etc. ) for 3-channel router RTL.

* Implementation of few verification projects in SV from scratch following Constrained, Random & Coverage Driven testing aspects. * RTL design (from scratch) - “GCD – Greatest Common Divider”. This was one of the projects verified by each member in the group.