Sohrab Jahani

I have designed and supervised the implementation of data processing protocols in wired networking such as OTN, SDH, GFP, Ethernet MAC, and RS-FEC at line rates from 100 Mbps to 40 Gbps. Selected professional skills: - RTL, synthesis, timing closure for wide data-paths clocking at 334+ MHz - Pin planning, IP integration, P&R optimization for multi-SLR Xilinx FPGAs - Interfaces such as 12G+ SerDes, DDR2/3 Controllers, etc. - Validation of large systems spanning multiple FPGAs

FPGA/ASIC design, DSP Architectures, Low Power Design, Computer Architecture, Microprocessors, Interfaces