YAHYA Farhadi

1-Conceptualized utilizing and clarified understanding of the Xilinx Vivado concepts such as special constraints, IO constraints, timing in terms of setup, hold, and pulse width, TCL, TTCL, XIT, more than 10 top-of-the-line analyses such as timing, congestion, complexity, clock domain crossing, power witch lead to increase throughput and less trial-and-error methods. 2- Completed more than 50 IPs in various fields such as UDP and TCP network IPs, PCIe, IO-based and JESD-based ADCs and DACs, Flash, SRAM

• Interpreted Vivado Design Suit and FPGA courses • Vivado Design Suite (Part1A): Synthesis to implementation in detail, Simulation, Xilinx IPs, TCL, Programming and Debugging, OOC, Processing orders, Attributes, and more concepts. • Vivado Design Suite (Part1B): IPs in detail, TTCL, Version Control • Vivado Design Suite (Part2): Floorplanning, Pipelining, High-end analysis including Timing in detail (setup, hold, pulse width), simultaneous switching noise, complexity, congestion, cross clock domain, power.