ARAVIND KARANTH

Flow development on SYNOPSYS tool suite for physical design activity. Involved in physical design and verification roles , on very complex sub designs of 22nm - state of the art - FPGA.

Involved in reliability verification of ASIC physical designs on some of the latest technology products which have made mark in industry by now ! ASIC Physical design and verification of various graphics designs using SYNOPSYS TOOLS. Analog layout design and verification using CADENCE and CALIBRE respectively.

As a Layout Design Engineer my tasks involved from analog layout design and verification, full chip integration and verification on a varied range of interesting products of CYPRESS SEMICONDUCTOR.

In this role of Associate Engineer, I was involved in Analog Physical Design tasks of some of the challenging analog circuits in TEXAS INSTRUMENTS - Bangalore - INDIA. Tasks covered a wide gamut of verticles from physical design to layout verification using CADENCE VIRTUSO and CALIBRE tools.